The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to a method and a structure thereof for more simply manufacturing a dynamic random access memory (DRAM) including both a PMOS transistor and NMOS transistor.
A DRAM is generally composed of a cell array portion having a plurality of NMOS transistors and capacitors corresponding thereto, and a peripheral circuit portion for driving the cell array portion. The peripheral circuit portion generally is made up of a plurality of CMOS transistors. However, as a device is further integrated, the distance between memory cells is narrowed and therefore a contact hole for exposing the source/drain area is decreased in size, thereby reducing the contact margin.
In order to improve such a problem, there was proposed a technique of forming a connection pad layer on the source/drain area of the plurality of NMOS transistors included in the cell array portion. In the case when the connection pad layer is formed only on the NMOS transistors included in the cell array portion, a step of forming the cell array portion and a step of forming the peripheral circuit portion must be divided, thus requiring many mask patterns. In addition, in the peripheral circuit portion as well as in the cell array portion, as the packing density of device is increased, a unit area where the device is formed is decreased. This demands more efficient utilization of the unit area.
For this reason, there was suggested a technique of forming the connection pad layer for increasing contact margin even on the source/drain area of the transistors included in the peripheral circuit portion. Here, a conventional semiconductor device which has both an NMOS transistor and PMOS transistor and in which the connection pad layer for securing the contact margin is formed on the entire source/drain area, will be discussed with reference to FIG. 1.
Referring to FIG. 1, a P-well 101 and an N-well 102 are selectively formed on a semiconductor substrate 100. In order to define a device isolation area and active area, a device isolating layer 103 such as a field oxide layer is selectively formed on P-well 101. In order to form a channel, n+ source/drain areas 105 and 106 are formed in the active area of P-well 101 at a predetermined interval. A gate insulating layer 115 is formed on the channel. A gate electrode 110 is formed on gate insulating layer 115. A cap insulating layer 112 is formed on gate electrode 110. A spacer insulating layer (spacer) 109a is formed on the sidewalls of the gate electrode 110. A connection pad layer (pad) 111a is formed respectively on n+ source/drain areas 105 and 106. As mentioned earlier, connection pad layer 111a is designed to increase contact margin so that one end is extended onto the top of cap insulating layer 112 and the other end onto the top of device isolating layer 103. Respective connection pad layers 111a are separately formed for electrical insulation, and are electrically insulated from gate electrode 110 by cap insulating layer 112 and spacer insulating layer 109a.
Similar to that of P-well 101, on N-well 102, the device isolating layer 103 is formed to define the active area of the device. In the active area, in order to form a channel, p+ source/drain areas 107 and 108 are formed at a predetermined interval. Gate insulating layer 115, gate electrode 110 and cap insulating layer 112 are sequentially formed on the channel. Spacer insulating layer 109b is formed on the sidewalls of gate electrode 110. Connection pad layer 111b is formed respectively on p+ source/drain areas 107 and 108.
On the PMOS transistor and NMOS transistor, there are formed an interlevel dielectric layer 113 having a plurality of openings for exposing connection pad layers 111a and 111b, and a plurality of electrodes 114 connected respectively to connection pad layers 111a and 111b. For instance, in a DRAM having a cell array portion composed of a plurality of NMOS transistors, the electrodes can correspond to bit lines or word lines.
Advantages of the conventional semiconductor device are as follows.
(1) The connection pad layer is formed on the entire active area including the source/drain area of the PMOS transistor and NMOS transistor, to thereby relax the design rule for contact to be formed.
(2) For a DRAM, the connection pad layer is formed on the peripheral circuit portion including the NMOS transistor and PMOS transistor as well as on the cell array portion including only the NMOS transistors, to thereby reduce step size.
(3) As the connection pad layer is introduced, the active area is reduced whereas the operation speed of device is increased.
Despite such advantages, in order to manufacture such a structure, there should be formed the connection pad layers to both the PMOS transistor and NMOS transistor. This inevitably increases the number of mask patterns.
For further discussion of the problem, a manufacturing process of the semiconductor device will be described below.
(1) First, a substrate 100 is provided and P-well 101 and N-well 102 are selectively formed thereon to selectively form device isolating layer 103 such as a field oxide layer.
(2) A thermal oxide layer is formed as a gate insulating layer on the overall surface of the resultant structure. Then, a first polysilicon layer for forming a gate electrode is formed thereon and an impurity is implanted. Thereafter, a first CVD insulating layer for forming a cap insulating layer is formed and a gate-mask pattern for defining the gate electrode is formed thereon. Using the gate-mask pattern, the first CVD insulating layer, polysilicon layer and thermal oxide layer are sequentially and selectively etched to thereby form cap insulating layer 112, gate electrode 110 and gate insulating layer 115 as shown in FIG. 1.
(3) An n- impurity is implanted on the resultant structure.
(4) A second CVD insulating layer is formed on the overall surface of the resultant structure. An NMOS-mask pattern for exposing an area where the NMOS transistor is to be formed is formed. The second CVD insulating layer formed on an area where the exposed NMOS transistor is to be formed is anisotropically etched to form spacer 109a on the sidewalls of gate electrode 110.
(5) A second polysilicon layer for forming the connection pad layer of NMOS transistor is formed.
(6) An n+ impurity is implanted to form n+ source/drain areas 105 and 106 of the NMOS transistor and simultaneously to dope the second polysilicon layer.
(7) An NMOS pad-mask pattern for defining the connection pad layer of NMOS transistor is formed. The second polysilicon layer is selectively etched by using the pattern to form connection pad layer 111a.
(8) The NMOS-mask pattern is removed to form a PMOS-mask pattern for exposing an area where the PMOS transistor is formed.
(9) The second CVD oxide layer left on the area where the PMOS transistor is to be formed is anisotropically etched to form spacer 109b on the sidewalls of gate electrode 110.
(10) A third polysilicon layer for forming the connection pad layer of PMOS transistor is formed and a p+ impurity is then implanted to form p+ source/drain areas 107 and 108 of NMOS transistor and simultaneously to dope the third polysilicon layer.
(11) A PMOS pad-mask pattern for defining the connection pad layer of PMOS transistor is formed. By using the pattern, the third polysilicon layer is selectively etched to form connection pad layer 111b.
(12) An interlevel dielectric layer 113 is formed on the overall surface of the resultant structure. In order to form a plurality of openings for exposing connection pad layers 111a and 111b, the interlevel dielectric layer is selectively etched by using a contact-mask pattern.
(13) A plurality of electrodes 114 respectively connected to connection pad layers 111a and 111b through the openings are formed.
In the above manufacturing method, if an n- impurity is implanted into the entire source/drain area of the NMOS transistor and PMOS transistor in step (3), the NMOS transistor has an LDD structure and thus has an improved characteristics. However, in this case, since a p-type conductive area is formed on the source/drain area of the PMOS transistor, although a p+ impurity is implanted later, a threshold voltage becomes extremely high to produce difficulty in driving.
Generally, in the case where there is no connection pad layer, an n- impurity is doped on the source/drain area of the PMOS transistor and a p+ impurity is doped later. By doing so, the n- doped area acts to preclude the diffusion of the p-type impurity, which exhibits a preferable effect.
However, as shown in FIG. 1, when the connection pad layer is formed on the source/drain area of PMOS transistor and then p+ impurity is implanted, the impurity cannot be implanted efficiently and the threshold voltage becomes extremely high as mentioned above. Meanwhile, when the p+ impurity is implanted heavily in order to reduce the threshold voltage of PMOS transistor, the depth of junction becomes severely deep. Moreover, since the diffusivity of boron (generally used as the p-type impurity) is very high, the punch-through of PMOS transistor is deteriorated.
In order to overcome these problems, there was proposed a method of forming an n- impurity-doped mask pattern to thereby dope the n- impurity only into the source/drain area of NMOS transistor in step (3). In this case, however, the number of mask patterns used during the manufacturing process is increased. A mask pattern generally is formed by photolithography and requires a great deal of cost and time, increasing the overall production cost of a semiconductor device, such that any increase in the number of mask patterns is very unfavorable.